GlobalDeffuncWinMes.as [ウインドウメッセージ定義命令]
;*******************************************************************************
; SetFSB Window Message Global Space Definition Function [2007.09.15]
; Programmed in HSP Ver3.1 ONION software(http://www.onionsoft.net/hsp/)
;
; 1. GetCulationData
; 2. CulationFreq(_nGear,_nDataN,_nDataM,_nDataDiv)
; 3. SetCulationData
; 4. SetFreqRange
; 5. SetControlRegister
; 6. GetPll()
; 7. SetPll()
; 8. ButtonFSB
;
;*******************************************************************************
;/Get Culation Data Definition Function
;--------+---------+---------+---------+---------+---------+---------+---------+
; CrFsbN,CrFsbM,CrPllbN,CrPllbM -> NumFsb,NumPci
;--------+---------+---------+---------+---------+---------+---------+---------+
#deffunc GetCulationData
; FsbGear,PllbGear,REF_Fsb,REF_Pci
switch iPLL_Type
case 0
case 1
case 0x81
case 2
case 3
case 0x84
case 7
case 8
iFsbGear=aFsbGearTbl(CR_CpuRatio())*CND(fGearUnitK,1000,1)
swbreak
case 5
case 6
iFsbGear=iPllbGearDt*CND(fGearUnitK,1000,1)
swbreak
swend
iPllbGear=iPllbGearDt*CND(fGearUnitK,1000,1)
iFsbRef=CND(fUltra,aFsbRefUTbl(CR_CpuRatio()),aFsbRefNTbl(CR_CpuRatio()))+iDivMA_Ofset
iPciRef=aPllbRefTbl(CR_PLLBRatio())+iDivMB_Ofset
; CPU,[DDR],AGP,PCI,PLLB clock divider ratio
iCpuDiv=aCpuDivTbl(CR_CpuRatio())
iAgpDiv=aAgpDivTbl(CR_AgpRatio())
iPciDiv=aPciDivTbl(CR_PciRatio())
iPllbDiv=aPllbDivTbl(CR_PLLBRatio())
switch iPLL_Type
case 5
case 6
iDdrDiv=aCpuDivTbl(CR_RamRatio())
swbreak
swend
; DDR Rate
switch iHostBridge
case Intel865P ;0x25708086
case Intel875P ;0x25788086
if (iGMCHC&0x0C030000)=0x00000000 : iDdrN=8 : iDdrM=3 ;?
if (iGMCHC&0x0C030000)=0x04000000 : iDdrN=8 : iDdrM=3
if (iGMCHC&0x0C030000)=0x08000000 : iDdrN=4 : iDdrM=1 ;?
if (iGMCHC&0x0C030000)=0x0C000000 : iDdrN=2 : iDdrM=1 ;?
if (iGMCHC&0x0C030000)=0x00010000 : iDdrN=2 : iDdrM=1
if (iGMCHC&0x0C030000)=0x04010000 : iDdrN=5 : iDdrM=2
if (iGMCHC&0x0C030000)=0x08010000 : iDdrN=3 : iDdrM=1 ;?
if (iGMCHC&0x0C030000)=0x0C010000 : iDdrN=2 : iDdrM=1 ;-
if (iGMCHC&0x0C030000)=0x00020000 : iDdrN=4 : iDdrM=3
if (iGMCHC&0x0C030000)=0x04020000 : iDdrN=8 : iDdrM=5
if (iGMCHC&0x0C030000)=0x08020000 : iDdrN=2 : iDdrM=1
if (iGMCHC&0x0C030000)=0x0C020000 : iDdrN=2 : iDdrM=1 ;-
if (iGMCHC&0x0C030000)=0x00030000 : iDdrN=2 : iDdrM=1 ;-
if (iGMCHC&0x0C030000)=0x04030000 : iDdrN=2 : iDdrM=1 ;-
if (iGMCHC&0x0C030000)=0x08030000 : iDdrN=2 : iDdrM=1 ;-
if (iGMCHC&0x0C030000)=0x0C030000 : iDdrN=2 : iDdrM=1 ;-
swbreak
case Intel850 ;0x25308086
iDdrN=CND(iMCHC&0x00000800,4,3) : iDdrM=1
swbreak
case Intel855PM ;0x33408086
iDdrN=8 : iDdrM=CND(iGMCHC&0x08000000,3,4)
swbreak
case Intel855GM ;0x35808086
switch iHPLLCC
case 0
iDdrN=8 : iDdrM=3
swbreak
case 7
iDdrN=10 : iDdrM=3
swbreak
default
iDdrN=2 : iDdrM=1
swbreak
swend
swbreak
case ViaKT400 ;0x31891106
iDdrN=iDRAMCCS>>20&7 : iDdrM=iPciDiv/iCpuDiv
swbreak
case ViaKT266 ;0x30991106
if (iDRAMCCS&0xC000)=0x0000 : iDdrN=2 : iDdrM=1 ;CPU=DRAM
if (iDRAMCCS&0xC000)=0x8000 : iDdrN=(iPciDiv/iCpuDiv-1)*2 : iDdrM=iPciDiv/iCpuDiv ;RAM=CPU-33.3MHz
if (iDRAMCCS&0xC000)=0x4000 : iDdrN=(iPciDiv/iCpuDiv+1)*2 : iDdrM=iPciDiv/iCpuDiv ;RAM=CPU+33.3MHz
if (iDRAMCCS&0xC000)=0xC000 : iDdrN=(iPciDiv/iCpuDiv+2)*2 : iDdrM=iPciDiv/iCpuDiv ;RAM=CPU+66.6MHz
swbreak
case Intel440BX ;0x71908086
case Intel440LX ;0x71808086
iDdrN=1 : iDdrM=1
swbreak
case ViaPro133 ;0x06911106
if (iDRAMCCS&0xC000)=0x0000 : iDdrN=1 : iDdrM=1 ;CPU=DRAM
if (iDRAMCCS&0xC000)=0x8000 : iDdrN=iPciDiv/iCpuDiv-1 : iDdrM=iPciDiv/iCpuDiv ;RAM=CPU-33.3MHz
if (iDRAMCCS&0xC000)=0x4000 : iDdrN=iPciDiv/iCpuDiv+1 : iDdrM=iPciDiv/iCpuDiv ;RAM=CPU+33.3MHz
if (iDRAMCCS&0xC000)=0xC000 : iDdrN=iPciDiv/iCpuDiv+2 : iDdrM=iPciDiv/iCpuDiv ;RAM=CPU+66.6MHz
swbreak
case SiS635
case SiS640
case SiS645
case SiS735
case SiS740 ;Fixed bug 20b8t
iDdrM=1 : if iGMCHC&0x40 : iDdrN=2 : else : iDdrN=1
swbreak
default
iDdrN=2 : iDdrM=1
swbreak
swend
if szPLLmodel="ICS951403CF" {
; if CR_RamRatio()=0 : 100:100
if CR_RamRatio()=1 : iDdrN=iDdrN*4 : iDdrM=iDdrM*3
if CR_RamRatio()=2 : iDdrN=iDdrN*3 : iDdrM=iDdrM*2
if CR_RamRatio()=3 : iDdrN=iDdrN*2 : iDdrM=iDdrM*3
; if CR_RamRatio()=4 : 133:133
if CR_RamRatio()=5 : iDdrN=iDdrN*4 : iDdrM=iDdrM*5
; if CR_RamRatio()=6 : 124:124
if CR_RamRatio()=7 : iDdrN=iDdrN*3 : iDdrM=iDdrM*4
}
; CPU,AGP,PCI Frequency
iFsFsb=aCpuFreqTbl(CND(CR_FsSource(),CR_FsIIc(),CR_FsHw()))
iFsAgp=aAgpFreqTbl(CND(CR_FsSource(),CR_FsIIc(),CR_FsHw()))
iFsPci=aPciFreqTbl(CND(CR_FsSource(),CR_FsIIc(),CR_FsHw()))
switch iPLL_Type
case 5
case 6
iFsDdr=aDdrFreqTbl(CND(CR_FsSource(),CR_FsIIc(),CR_FsHw()))
swbreak
swend
; CrFsbN,CrFsbM,CrPllbN,CrPllbM
switch iPLL_Type
case 0
case 5
iCrFsbN=(CR_DivN07A()|CR_DivN8A()|CR_DivN9A())+iDivNA_Ofset : iCrFsbM=CR_DivMA()+iDivMA_Ofset : iCrPllbN=(CR_DivN07B()|CR_DivN8B()|CR_DivN9B())+iDivNB_Ofset : iCrPllbM=CR_DivMB()+iDivMB_Ofset
swbreak
case 1
case 6
case 0x81
iCrFsbN=(CR_DivN29A()|CR_DivN01A())+iDivNA_Ofset : iCrFsbM=CR_DivMA()+iDivMA_Ofset : iCrPllbN=(CR_DivN29B()|CR_DivN01B())+iDivNB_Ofset : iCrPllbM=CR_DivMB()+iDivMB_Ofset
swbreak
case 2
iCrFsbN=(CR_DivN07A()|CR_DivN8A()|CR_DivN9A())+iDivNA_Ofset : iCrFsbM=CR_DivMA()+iDivMA_Ofset : iCrPllbN=(CR_DivN07B()|CR_DivN8B()|CR_DivN9B())+iDivNB_Ofset : iCrPllbM=iDivMB_Fix+iDivMB_Ofset
swbreak
case 3
iCrFsbN=(CR_DivN07A()|CR_DivN8A()|CR_DivN9A())+iDivNA_Ofset : iCrFsbM=iDivMA_Fix+iDivMA_Ofset : iCrPllbN=(CR_DivN07B()|CR_DivN8B()|CR_DivN9B())+iDivNB_Ofset : iCrPllbM=iDivMB_Fix+iDivMB_Ofset
swbreak
case 0x84
iCrFsbN=(CR_DivN29A()|CR_DivN01A())+iDivNA_Ofset : iCrFsbM=iDivMA_Fix+iDivMA_Ofset : iCrPllbN=(CR_DivN29B()|CR_DivN01B())+iDivNB_Ofset : iCrPllbM=iDivMB_Fix+iDivMB_Ofset
swbreak
case 7
iCrFsbN=(CR_DivN07A()|CR_DivN8A()|CR_DivN9A()|CR_DivN10A())+iDivNA_Ofset : iCrFsbM=CR_DivMA()+iDivMA_Ofset : iCrPllbN=(CR_DivN07B()|CR_DivN8B()|CR_DivN9B())+iDivNB_Ofset : iCrPllbM=iDivMB_Fix+iDivMB_Ofset
swbreak
swend
; NumFsb,NumPci
iNumFsb=CND(CR_MnProgEn(),iCrFsbN*iFsbRef/iCrFsbM-iDivNA_Ofset,iFsbRef*iFsFsb*iCpuDiv*10/iFsbGear-iDivNA_Ofset)
iNumPci=CND(CR_MnProgEn()|aAgpSelTbl(CR_nAgpFS())=1|aPciSelTbl(CR_nPciFS())=1,iCrPllbN*iPciRef/iCrPllbM-iDivNB_Ofset,iFsPci*iPciRef*iPllbDiv*10/iPllbGear-iDivNB_Ofset)
return
;/Culation Frequency Definition Function
;--------+---------+---------+---------+---------+---------+---------+---------+
; _nGear,_nDataN,_nDataM,_nDataDiv -> Frequency
;--------+---------+---------+---------+---------+---------+---------+---------+
#defcfunc CulationFreq int _nGear,int _nDataN, int _nDataM, int _nDataDiv
return double(_nGear)*_nDataN/(_nDataM*_nDataDiv*1000)
;/Set Culation Data Definition Function
;--------+---------+---------+---------+---------+---------+---------+---------+
; dCalcFsbFrq,dCalcDdrFrq,dCalcAgpFrq,dCalcPciFrq
;--------+---------+---------+---------+---------+---------+---------+---------+
#deffunc SetCulationData int _fSelFsb, int _nFSB, int _nPCI
if CR_MnProgEn()|_fSelFsb {
dCalcFsbFrq=CulationFreq(iFsbGear,CND(_fSelFsb,_nFSB+iDivNA_Ofset,iCrFsbN),CND(_fSelFsb,iFsbRef,iCrFsbM),iCpuDiv)
switch iPLL_Type
case 5
case 6
dCalcDdrFrq=CulationFreq(iFsbGear,CND(_fSelFsb,_nFSB+iDivNA_Ofset,iCrFsbN),CND(_fSelFsb,iFsbRef,iCrFsbM),iDdrDiv)*iDdrN/iDdrM
swbreak
default
dCalcDdrFrq=dCalcFsbFrq*iDdrN/iDdrM
swbreak
swend
switch aAgpSelTbl( CND(_fSelFsb, Set_nAgpFS(), CR_nAgpFS()) )
case 0 ;PLLfsb
dCalcAgpFrq=CulationFreq(iFsbGear,CND(_fSelFsb,_nFSB+iDivNA_Ofset,iCrFsbN),CND(_fSelFsb,iFsbRef,iCrFsbM),iAgpDiv)
swbreak
case 1 ;PLLB
dCalcAgpFrq=CulationFreq(iPllbGear,CND(_fSelFsb,_nPCI+iDivNB_Ofset,iCrPllbN),CND(_fSelFsb,iPciRef,iCrPllbM),iPllbDiv)*CND(fPllAgp,2,3)
swbreak
case 2 ;FsAgp
dCalcAgpFrq=double(iFsAgp)/100
swbreak
case 3 ;fix
dCalcAgpFrq=double(aFixFreqTbl(CND(_fSelFsb,Set_nFixFS(),CR_nFixFS())))*CND(fPllAgp,2,3)/100
swbreak
swend
switch aPciSelTbl( CND(_fSelFsb, Set_nPciFS(), CR_nPciFS()) )
case 0 ;PLLfsb
dCalcPciFrq=CulationFreq(iFsbGear,CND(_fSelFsb,_nFSB+iDivNA_Ofset,iCrFsbN),CND(_fSelFsb,iFsbRef,iCrFsbM),iPciDiv)
swbreak
case 1 ;PLLB
dCalcPciFrq=CulationFreq(iPllbGear,CND(_fSelFsb,_nPCI+iDivNB_Ofset,iCrPllbN),CND(_fSelFsb,iPciRef,iCrPllbM),iPllbDiv)
swbreak
case 2 ;FsPci
dCalcPciFrq=double(iFsPci)/100
swbreak
case 3 ;fix
dCalcPciFrq=double(aFixFreqTbl(CND(_fSelFsb,Set_nFixFS(),CR_nFixFS())))/100
swbreak
swend
} else {
dCalcFsbFrq=double(iFsFsb)/100
switch iPLL_Type
case 5
case 6
dCalcDdrFrq=double(iFsDdr)*iDdrN/(iDdrM*100)
swbreak
default
dCalcDdrFrq=double(iFsFsb)*iDdrN/(iDdrM*100)
swbreak
swend
switch aAgpSelTbl( CND(_fSelFsb, Set_nAgpFS(), CR_nAgpFS()) )
case 0 ;PLLfsb
case 2 ;iFsAgp
dCalcAgpFrq=double(iFsAgp)/100
swbreak
case 1 ;PLLB
dCalcAgpFrq=CulationFreq(iPllbGear,CND(_fSelFsb,_nPCI+iDivNB_Ofset,iCrPllbN),CND(_fSelFsb,iPciRef,iCrPllbM),iPllbDiv)*CND(fPllAgp,2,3)
swbreak
case 3 ;fix
dCalcAgpFrq=double(aFixFreqTbl(CND(_fSelFsb,Set_nFixFS(),CR_nFixFS())))*CND(fPllAgp,2,3)/100
swbreak
swend
switch aPciSelTbl( CND(_fSelFsb, Set_nPciFS(), CR_nPciFS()) )
case 0 ;PLLfsb
case 2 ;iFsPci
dCalcPciFrq=double(iFsPci)/100
swbreak
case 1 ;PLLB
dCalcPciFrq=CulationFreq(iPllbGear,CND(_fSelFsb,_nPCI+iDivNB_Ofset,iCrPllbN),CND(_fSelFsb,iPciRef,iCrPllbM),iPllbDiv)
swbreak
case 3 ;fix
dCalcPciFrq=double(aFixFreqTbl(CND(_fSelFsb,Set_nFixFS(),CR_nFixFS())))/100
swbreak
swend
}
return
;/Set Frequency Range Definition Function
;--------+---------+---------+---------+---------+---------+---------+---------+
#deffunc SetFreqRange int _fMn, int _iRngCmb
switch _iRngCmb
case 0
if _fMn {
iPrmFsbTrbOfs=PLLcodeWord(Getupdnpos(hwTrbFsbMaxUpdn),iFsbTrbOfsU) ;
aPrmFsbRefNTbl(CR_CpuRatio())=PLLcodeByte(Getupdnpos(hwPllRefUpd),aFsbRefUTbl(CR_CpuRatio()),aPllbRefTbl(CR_CpuRatio()),aPllbDivTbl(CR_CpuRatio()))
}
dCalcMaxFrq=CulationFreq(iFsbGear,iFsbTrbMax-iFsbTrbOfsN+iDivNA_Ofset,aFsbRefNTbl(CR_CpuRatio())+iDivMA_Ofset,iCpuDiv)
dCalcMinFrq=CulationFreq(iFsbGear,iFsbTrbMin-iFsbTrbOfsN+iDivNA_Ofset,aFsbRefNTbl(CR_CpuRatio())+iDivMA_Ofset,iCpuDiv)
settext hwRngFsbMinStc,strf("%3.1f",dCalcMinFrq)+"MHz"
settext hwRngFsbMaxStc,strf("%3.1f",dCalcMaxFrq)+"MHz"
settext hwTrbFsbMaxStc,str(iFsbTrbMax-iFsbTrbOfsN)
setupdnrng hwTrbFsbMaxUpdn,0,iFsbTrbMin
setupdnpos hwTrbFsbMaxUpdn,iFsbTrbOfsN
setupdnrng hwPllRefUpd,iFsbRefMin,iFsbRefMax
setupdnpos hwPllRefUpd,aFsbRefNTbl(CR_CpuRatio())
settext hwPllRefStc,str(aFsbRefNTbl(CR_CpuRatio()))
settext hwPllGearStc,str(iFsbGear)
swbreak
case 1
if _fMn {
iPrmFsbTrbOfs=PLLcodeWord(iFsbTrbOfsN,Getupdnpos(hwTrbFsbMaxUpdn)) ;
aPrmFsbRefNTbl(CR_CpuRatio())=PLLcodeByte(aFsbRefNTbl(CR_CpuRatio()),Getupdnpos(hwPllRefUpd),aPllbRefTbl(CR_CpuRatio()),aPllbDivTbl(CR_CpuRatio()))
}
dCalcMaxFrq=CulationFreq(iFsbGear,iFsbTrbMax-iFsbTrbOfsU+iDivNA_Ofset,aFsbRefUTbl(CR_CpuRatio())+iDivMA_Ofset,iCpuDiv)
dCalcMinFrq=CulationFreq(iFsbGear,iFsbTrbMin-iFsbTrbOfsU+iDivNA_Ofset,aFsbRefUTbl(CR_CpuRatio())+iDivMA_Ofset,iCpuDiv)
settext hwRngFsbMinStc,strf("%3.1f",dCalcMinFrq)+"MHz"
settext hwRngFsbMaxStc,strf("%3.1f",dCalcMaxFrq)+"MHz"
settext hwTrbFsbMaxStc,str(iFsbTrbMax-iFsbTrbOfsU)
setupdnrng hwTrbFsbMaxUpdn,0,iFsbTrbMin
setupdnpos hwTrbFsbMaxUpdn,iFsbTrbOfsU
setupdnrng hwPllRefUpd,iFsbRefMin,iFsbRefMax
setupdnpos hwPllRefUpd,aFsbRefUTbl(CR_CpuRatio())
settext hwPllRefStc,str(aFsbRefUTbl(CR_CpuRatio()))
settext hwPllGearStc,str(iFsbGear)
swbreak
case 2
if _fMn {
iPrmPllbGear=PLLcodeWord(iPllbGearDt,Getupdnpos(hwTrbFsbMaxUpdn)) ;PllbGear, PciTrbOfs
aPrmFsbRefNTbl(CR_PLLBRatio())=PLLcodeByte(aFsbRefNTbl(CR_PLLBRatio()),aFsbRefUTbl(CR_PLLBRatio()),Getupdnpos(hwPllRefUpd),aPllbDivTbl(CR_PLLBRatio()))
}
dCalcMaxFrq=CulationFreq(iPllbGear,iPciTrbMax-iPciTrbOfs+iDivNB_Ofset,aPllbRefTbl(CR_PLLBRatio())+iDivMB_Ofset,iPllbDiv)*CND(fPllAgp,1,3)
dCalcMinFrq=CulationFreq(iPllbGear,iPciTrbMin-iPciTrbOfs+iDivNB_Ofset,aPllbRefTbl(CR_PLLBRatio())+iDivMB_Ofset,iPllbDiv)*CND(fPllAgp,1,3)
settext hwRngFsbMinStc,strf("%3.1f",dCalcMinFrq)+"MHz"
settext hwRngFsbMaxStc,strf("%3.1f",dCalcMaxFrq)+"MHz"
settext hwTrbFsbMaxStc,str(iPciTrbMax-iPciTrbOfs)
setupdnrng hwTrbFsbMaxUpdn,0,iPciTrbMin
setupdnpos hwTrbFsbMaxUpdn,iPciTrbOfs
setupdnrng hwPllRefUpd,iPciRefMin,iPciRefMax
setupdnpos hwPllRefUpd,aPllbRefTbl(CR_PLLBRatio())
settext hwPllRefStc,str(aPllbRefTbl(CR_PLLBRatio()))
settext hwPllGearStc,str(iPllbGear)
swbreak
swend
return
;/Set Control Register Definition Function
;--------+---------+---------+---------+---------+---------+---------+---------+
#define DT_DivMA ((iFsbRef-iDivMA_Ofset)&iDivMA_Unmask)
#define DT_DivMB ((iPciRef-iDivMB_Ofset)&iDivMB_Unmask)
#define DT_DivN07A (_nFSB&iDivN07A_Unmask)
#define DT_DivN8A ((_nFSB&0x100)/0x100*iDivN8A_Unmask)
#define DT_DivN9A ((_nFSB&0x200)/0x200*iDivN9A_Unmask)
#define DT_DivN10A ((_nFSB&0x400)/0x400*iDivN10A_Unmask)
#define DT_DivN07B (_nPCI&iDivN07B_Unmask)
#define DT_DivN8B ((_nPCI&0x100)/0x100*iDivN8B_Unmask)
#define DT_DivN9B ((_nPCI&0x200)/0x200*iDivN9B_Unmask)
#define DT_DivN29A (_nFSB>>iDivN29A_left&iDivN29A_Unmask)
#define DT_DivN01A CND(iDivN01A_Unmask=5,(_nFSB&1)*5<<iDivN01A_right,_nFSB<<iDivN01A_right&iDivN01A_Unmask)
#define DT_DivN29B (_nPCI>>iDivN29B_left&iDivN29B_Unmask)
#define DT_DivN01B (_nPCI<<iDivN01B_right&iDivN01B_Unmask)
#define DT_Agp0 (Set_nAgpFS()&1)*iAgpFSA_Unmask
#define DT_Agp1 (Set_nAgpFS()&2)/2*iAgpFSB_Unmask
#define DT_Agp2 (Set_nAgpFS()&4)/4*iAgpFSC_Unmask
#define DT_Pci0 (Set_nPciFS()&1)*iPciFSA_Unmask
#define DT_Pci1 (Set_nPciFS()&2)/2*iPciFSB_Unmask
#define DT_Pci2 (Set_nPciFS()&4)/4*iPciFSC_Unmask
#define DT_Fix0 (Set_nFixFS()&1)*iFixFSA_Unmask
#define DT_Fix1 (Set_nFixFS()&2)/2*iFixFSB_Unmask
#define DT_Bit0 (Set_nFixBit()&1)*iFixBitA_Unmask
#define DT_Bit1 (Set_nFixBit()&2)/2*iFixBitB_Unmask
#define SetControlRegister(%1,%2=0,%3=0) _SetControlRegister %1,%2,%3
#deffunc _SetControlRegister int _fMnProg, int _nFSB, int _nPCI
if _fMnProg {
switch iPLL_Type
case 0
case 1
case 2
case 3
case 5
case 6
case 7
case 0x81
case 0x84
aCR(iMnProgEn_IIc)=CND(iMnProgEn_Exor,aCR(iMnProgEn_IIc)&(iMnProgEn_Unmask^0xFF),aCR(iMnProgEn_IIc)|iMnProgEn_Unmask)
aCR(iAgpFSA_IIc)=aCR(iAgpFSA_IIc)&(iAgpFSA_Unmask^0xFF)|DT_Agp0
aCR(iAgpFSB_IIc)=aCR(iAgpFSB_IIc)&(iAgpFSB_Unmask^0xFF)|DT_Agp1
aCR(iAgpFSC_IIc)=aCR(iAgpFSC_IIc)&(iAgpFSC_Unmask^0xFF)|DT_Agp2
aCR(iPciFSA_IIc)=aCR(iPciFSA_IIc)&(iPciFSA_Unmask^0xFF)|DT_Pci0
aCR(iPciFSB_IIc)=aCR(iPciFSB_IIc)&(iPciFSB_Unmask^0xFF)|DT_Pci1
aCR(iPciFSC_IIc)=aCR(iPciFSC_IIc)&(iPciFSC_Unmask^0xFF)|DT_Pci2
aCR(iFixFSA_IIc)=aCR(iFixFSA_IIc)&(iFixFSA_Unmask^0xFF)|DT_Fix0
aCR(iFixFSB_IIc)=aCR(iFixFSB_IIc)&(iFixFSB_Unmask^0xFF)|DT_Fix1
swbreak
swend
} else {
switch iPLL_Type
case 7
aCR(iDivN10A_IIc)=aCR(iDivN10A_IIc)&(iDivN10A_Unmask^0xFF)|DT_DivN10A
case 0
case 2
case 3
case 5
aCR(iDivMA_IIc)=aCR(iDivMA_IIc)&(iDivMA_Unmask^0xFF)|DT_DivMA
aCR(iDivN07A_IIc)=aCR(iDivN07A_IIc)&(iDivN07A_Unmask^0xFF)|DT_DivN07A
aCR(iDivN8A_IIc)=aCR(iDivN8A_IIc)&(iDivN8A_Unmask^0xFF)|DT_DivN8A
aCR(iDivN9A_IIc)=aCR(iDivN9A_IIc)&(iDivN9A_Unmask^0xFF)|DT_DivN9A
aCR(iDivMB_IIc)=aCR(iDivMB_IIc)&(iDivMB_Unmask^0xFF)|DT_DivMB
aCR(iDivN07B_IIc)=aCR(iDivN07B_IIc)&(iDivN07B_Unmask^0xFF)|DT_DivN07B
aCR(iDivN8B_IIc)=aCR(iDivN8B_IIc)&(iDivN8B_Unmask^0xFF)|DT_DivN8B
aCR(iDivN9B_IIc)=aCR(iDivN9B_IIc)&(iDivN9B_Unmask^0xFF)|DT_DivN9B
if szPLLmodel="ICS954123CGLF" : aCR(iDivN07A_IIc+1)=aCR(iDivN07A_IIc) : aCR(iDivN07A_IIc+2)=aCR(iDivN07A_IIc)
swbreak
case 0x84
case 0x81
aCR(0x1F)=aCR(0x1F)|1
if szPLLmodel="RTM866-485" : aCR(0x1D)=aCR(0x1D)&0x0F|0x30
case 1
case 6
aCR(iDivMA_IIc)=aCR(iDivMA_IIc)&(iDivMA_Unmask^0xFF)|DT_DivMA
aCR(iDivN01A_IIc)=CND(iDivN01A_Unmask=5,aCR(iDivN01A_IIc)&(0x0F<<iDivN01A_right^0xFF),aCR(iDivN01A_IIc)&(iDivN01A_Unmask^0xFF))|DT_DivN01A
aCR(iDivN29A_IIc)=aCR(iDivN29A_IIc)&(iDivN29A_Unmask^0xFF)|DT_DivN29A
aCR(iDivMB_IIc)=aCR(iDivMB_IIc)&(iDivMB_Unmask^0xFF)|DT_DivMB
aCR(iDivN01B_IIc)=aCR(iDivN01B_IIc)&(iDivN01B_Unmask^0xFF)|DT_DivN01B
aCR(iDivN29B_IIc)=aCR(iDivN29B_IIc)&(iDivN29B_Unmask^0xFF)|DT_DivN29B
if szPLLmodel="ICS9LPRS552AGLF" : aCR(0x17)=aCR(iDivN29A_IIc),aCR(iDivN29A_IIc),aCR(iDivN29A_IIc) : aCR(0x14)=aCR(0x14)|0x80
swbreak
swend
aCR(iFixBitA_IIc)=aCR(iFixBitA_IIc)&(iFixBitA_Unmask^0xFF)|DT_Bit0
aCR(iFixBitB_IIc)=aCR(iFixBitB_IIc)&(iFixBitB_Unmask^0xFF)|DT_Bit1
}
return
;/PLL Definition Function
;--------+---------+---------+---------+---------+---------+---------+---------+
; GetPll(),SetPll()
; * _tmp!0 -> SMBus Error
;--------+---------+---------+---------+---------+---------+---------+---------+
#define global ctype GetPll(%1=0) Pll(%1)
#define global ctype SetPll(%1=1) Pll(%1)
#defcfunc Pll int _fMode
do
;Asusのお呪い
_iTmp=SMBusPll(iSMBusCtl,iSMBadr,iAsus) : if _iTmp : _break ;SMBusをPLL-ICにセット
;SMBus
switch _fMode
case 0 ;GetPll()
if iSmbCmb|(iPLL_Type>>7) { ;Byte Read 48byte
repeat CND(iPLL_ReadByte=-1,0x30,iPLL_ReadByte)
iByte=cnt : _iTmp=GetByteRTM(aCR(cnt),iSMBusCtl,iSMBadr,0xD2,0x80|cnt)
; iByte=cnt : _iTmp=GetByteICS(aCR(cnt),iSMBusCtl,iSMBadr,0xD2,0x80|cnt)
if _iTmp : break
iByte++
loop
} else { ;Block Read
_iTmp=GetBlockPll(aCR,iSMBusCtl,iSMBadr,iByte)
}
swbreak
case 1 ;SetPll()
_iTmp=SetBlockPll(aCR,iSMBusCtl,iSMBadr,iByte)
swbreak
swend
;Asusのお呪い
_iTmp=SMBusRtn(iSMBusCtl,iSMBadr,iAsus) ;SMBusを元に戻す
until
return _iTmp
;/Button & Window Message Definition Function //ボタン処理
;--------+---------+---------+---------+---------+---------+---------+---------+
; ButtonFSB nGetFSB/nSetFSB/nApplyFSB/nRefresh
;--------+---------+---------+---------+---------+---------+---------+---------+
#deffunc ButtonFSB int _nPrm
if _nPrm!nRefresh : SetfsbObjDisable _nPrm
do
if _nPrm=nGetFSB|_nPrm=nSetFSB { ;PLL-ICデータのブロックリード
#if TEST
iByte=CND(iReadByte_Min!-1,iCrByteCount,CND(iPLL_ReadByte!-1,iPLL_ReadByte,0x30))
#else
if GetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
if _nPrm=nGetFSB {
if szPLLmodel="CY28551LFXC" & (aCR(18)&0x20)!0 {
aCR(iDivN07A_IIc)=aCR(10) : aCR(iDivN8A_IIc)=aCR(iDivN8A_IIc)&(iDivN8A_Unmask^0xFF)|(aCR(9)&0x20)/0x20*iDivN8A_Unmask
aCR(18)=aCR(18)&0xDF
#if TEST
aSleep 100
#else
iByte=CND(iPLL_WriteByte!-1,iPLL_WriteByte,iByte)
if SetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
}
if szPLLmodel="PLL diagnosis" { ;PLL diagnosis
aSleep 300
settext hwCurFrqStc,"Unknown"
settext hwSelFrqStc,"Unknown"
settrackrng hwFsbTrb,0,1
settrackrng hwPciTrb,0,1
settext hwNumFsbStc,"/"
settext hwNumPciStc,"/"
_break
}
if CND(iReadByte_Min!-1,iByte<iReadByte_Min,0) {
if strmid(szPLLmodel,0,3)="ICS" {
iCrByteCount=iReadByte_Min
if SetByteICS(iCrByteCount,iSMBusCtl,iSMBadr,0xD2,0x80|iByteCount_IIc) : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#if TEST
iByte=CND(iReadByte_Min!-1,iCrByteCount,CND(iPLL_ReadByte!-1,iPLL_ReadByte,0x30))
#else
if GetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
if CND(iReadByte_Min!-1,iByte<iReadByte_Min,0) : iSetFsbFlg|=ErrPLLbyte : _break
} else {
iSetFsbFlg|=ErrPLLbyte : _break
}
}
if CND(iPLL_VenderID!0xFF,CR_VenderID()!iPLL_VenderID,0) : iSetFsbFlg|=ErrPLLid : _break ;PLL VenderID error
if CND(iPLL_ReadByte!-1,iByte!iPLL_ReadByte,0) {
if szPLLmodel="RTM520-39D" { ;PLL RTM520-39D
aCR(6)=0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF
iByte=0x11 : aCR(16)=1
} else {
iCrByteCount=iPLL_ReadByte
if iByte=iReadByte_Min : iByte=iReadByte_Min+1
if iByte>iPLL_ReadByte : iByte=iPLL_ReadByte
}
#if TEST
aSleep 100 : iByte=CND(iReadByte_Min!-1,iCrByteCount,CND(iPLL_ReadByte!-1,iPLL_ReadByte,0x30))
#else
if SetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
if GetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
}
if szPLLmodel="RTM520-39D" {
if (iHostBridge=Intel440BX)&((aCR(0)&0x70)!0x60) : iSetFsbFlg|=ErrRTM : _break ;RTM error
}
}
if CND(iPLL_ReadByte!-1,iByte!iPLL_ReadByte,0) : iSetFsbFlg|=ErrPLLbyte : _break ;PLL error
}
; test
; iByte=1 : if SetByteICS(iByte,iSMBusCtl,iSMBadr,0xD2,0x80|iByteCount_IIc) : iByte=iByte
; if GetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
if _nPrm!nRefresh : aSleep 300
if _nPrm=nGetFSB|_nPrm=nRefresh{
settrackrng hwFsbTrb,CND(fUltra,iFsbTrbMin-iFsbTrbOfsU,iFsbTrbMin-iFsbTrbOfsN),CND(fUltra,iFsbTrbMax-iFsbTrbOfsU,iFsbTrbMax-iFsbTrbOfsN)
clrtracktic hwFsbTrb
repeat (iFsbTrbMax-iFsbTrbMin)/((iFsbTrbMax+1)/256)-1 : settrackmrk hwFsbTrb,CND(fUltra,iFsbTrbMin-iFsbTrbOfsU,iFsbTrbMin-iFsbTrbOfsN)+cnt*((iFsbTrbMax+1)/256)+((iFsbTrbMax+1)/256) : loop ;トラックバー目盛
setupdnrng hwFsbUpd,CND(fUltra,iFsbTrbMin-iFsbTrbOfsU,iFsbTrbMin-iFsbTrbOfsN),CND(fUltra,iFsbTrbMax-iFsbTrbOfsU,iFsbTrbMax-iFsbTrbOfsN)
settrackrng hwPciTrb,iPciTrbMin-iPciTrbOfs,iPciTrbMax-iPciTrbOfs
clrtracktic hwPciTrb
repeat (iPciTrbMax-iPciTrbMin)/((iPciTrbMax+1)/128) : settrackmrk hwPciTrb,iPciTrbMin-iPciTrbOfs+cnt*((iPciTrbMax+1)/128)+((iPciTrbMax+1)/128) : loop ;トラックバー目盛
setupdnrng hwPciUpd,iPciTrbMin-iPciTrbOfs,iPciTrbMax-iPciTrbOfs
}
if _nPrm=nSetFSB|_nPrm=nApplyFSB {
if szPLLmodel="RTM876-660" | szPLLmodel="RTM362-210" {
if szPLLmodel="RTM876-660" : aCR(0x10)=aCR(0x10)|1
if szPLLmodel="RTM362-210" & (aCR(0x10)&0x83^0x83)!0 : aCR(0x10)=aCR(0x10)&0x7C|0x83
#if TEST
aSleep 100
#else
iByte=0x11
if SetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
}
if _nPrm=nSetFSB : SetControlRegister 0,Gettrackpos(hwFsbTrb),Gettrackpos(hwPciTrb)
if _nPrm=nApplyFSB : repeat iByte : aCR(cnt)=HEX(Getlsttext(hwCrLst(cnt))) : loop
#if TEST
aSleep 100
#else
iByte=CND(iPLL_WriteByte!-1,iPLL_WriteByte,iByte)
if SetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
if _nPrm=nSetFSB & (CR_MnProgEn()=0 | Set_nAgpFS()!CR_nAgpFS() | Set_nPciFS()!CR_nPciFS() | Set_nFixFS()!CR_nFixFS()) {
SetControlRegister 1,0,0
#if TEST
aSleep 100
#else
if SetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
}
if szPLLmodel="CV122CPVG" {
#if TEST
aSleep 100
#else
aCR(27)=aCR(27)|0xA0
if SetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
repeat 200
#if TEST
iByte=CND(iReadByte_Min!-1,iCrByteCount,CND(iPLL_ReadByte!-1,iPLL_ReadByte,0x30)) : aCR(6)=aCR(6)|0x40
#else
if GetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
if aCR(6)&0x40 : break
loop
if (aCR(6)&0x40)!0x40 : iSetFsbFlg|=ErrIDT : _break ;IDT error
#if TEST
aSleep 100 : aCR(6)=aCR(6)&0xBF
#else
aCR(27)=aCR(27)&0x5F
if SetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
}
if szPLLmodel="RTM520-39D" {
#if TEST
aCR(0x10)=1
#else
if SetBytePLL(aCR(0x1F),iSMBusCtl,iSMBadr,0xD2,0x1F) : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
aCR(0x10)=1 : if SetBytePLL(aCR(0x10),iSMBusCtl,iSMBadr,0xD2,0x10) : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
}
#if TEST
aSleep 100 : iByte=CND(iReadByte_Min!-1,iCrByteCount,CND(iPLL_ReadByte!-1,iPLL_ReadByte,0x30))
#else
if GetPll() : iSetFsbFlg|=ErrSMBus : _break ;SMBus error
#endif
if _nPrm=nSetFSB & CND(iPLL_ReadByte!-1,iByte!iPLL_ReadByte,0) : iSetFsbFlg|=ErrPLLbyte : _break ;PLL error
}
GetCulationData
settrackpos hwFsbTrb,iNumFsb
setupdnpos hwFsbUpd,iNumFsb
settrackpos hwPciTrb,iNumPci
setupdnpos hwPciUpd,iNumPci
settext hwNumFsbStc,str(iNumFsb-CND(fUltra,iFsbTrbMin-iFsbTrbOfsU,iFsbTrbMin-iFsbTrbOfsN))+"/"+str(iFsbTrbMax-iFsbTrbMin)
if iDivN07B_Unmask : settext hwNumPciStc,str(iNumPci-(iPciTrbMin-iPciTrbOfs))+"/"+str(iPciTrbMax-iPciTrbMin) : else : settext hwNumPciStc,"/"
SetCulationData 0,0,0
settext hwCurFrqStc,strf("%3.1f",dCalcFsbFrq)+"/"+strf("%3.1f",dCalcDdrFrq)+"/"+strf("%3.1f",dCalcAgpFrq)+"/"+strf("%3.1f",dCalcPciFrq)+"MHz"
SetCulationData 1,iNumFsb,iNumPci
settext hwSelFrqStc,strf("%3.1f",dCalcFsbFrq)+"/"+strf("%3.1f",dCalcDdrFrq)+"/"+strf("%3.1f",dCalcAgpFrq)+"/"+strf("%3.1f",dCalcPciFrq)+"MHz"
if _nPrm=nGetFSB {
SetFreqRange 0, iRngCmb
objenable hwTrbFsbMaxUpdn,1
if iRngCmb=2 & iPciRefMin=iPciRefMax : objenable hwPllRefUpd,0 : else : objenable hwPllRefUpd : objreshow hwPllRefUpd
if iRngCmb=2 & iPciTrbMin=iPciTrbMax : objenable hwTrbFsbMaxUpdn,0 : else : objenable hwTrbFsbMaxUpdn : objreshow hwTrbFsbMaxUpdn
}
until ; 20b5
if _nPrm=nGetFSB : settext hwCtlRegGbx," PLL Control Registers --- Byte Count "+StrUpper(strf("%02x",iByte))+"h("+strf("%02d",iByte)+") --- " ; 20b5
repeat 0x30
lstreset hwCrLst(cnt)
if cnt<iByte : lstaddstring hwCrLst(cnt),StrUpper(strf("%02x",aCR(cnt)))
loop
repeat 0x10
lstreset hwSmbLst(cnt) : lstaddstring hwSmbLst(cnt),StrUpper(strf("%02x",io_inp(iSMBadr+cnt)))
loop
settext hwOfsStc,""
settext hwHexEdt,""
settext hwBinEdt,""
if _nPrm!nRefresh {
SetfsbObjEnable 0
aSleep 50
settext hwCurCpuStc,strf("%0.1f",Getfreq(Getupdnpos(hwSelTmrUpd)))+"MHz"
objenable hwCurCpuStc,1 ;"Current CPU" static control
}
return
;------------------------------------------------------------------------------